Output Stage Design and Analysis in LTSpice

I've used the past weeks to come up with an output stage for the e-stim unit. I want to go for a high-voltage, low-current pulsed output. For this output, I want to be able to control pulse level and width/frequency. An LTSpice model of my basic design for one channel of the output stage can be seen below.

Starting on the top left and right, a digital PWM signal at half the pulse width and with the desired duty cycle is expected on Vdir and its inverse on Vdirinv. The Arduino Due has four PWM channels each with an output pin and an inverted output pin, called PWMH4, PWML4, ..., PWMH7, PWML7, which may be used here.

The 2N7002 transistors open and close with the PWM signal and are used in a Darlington configuration to drive the IRF9Z power MOSFETs, for which a gate voltage of 3.3V would be too small. The two MOSFETs in turn operate the two halves of the secondary side of a transformer, with center tap connected to the stim supply voltage V12. This way, the transformer is used to step up voltage and step down current. Using only one half on the secondary side at a time, and driving currents towards the center tap guarantees a zero net current flow over one PWM period. Diode D2 protects from overvoltages due to reverse currents that occur when the inductors discharge.

On the lower right, the standard test load resembling the human body, see [3], can be seen connected to the transformer's primary side. LTSpice also demands that the load be grounded. After some reading on [1], I decided to use Xicon 42TU003 transformers [2] which offer a 1:12 step-up ratio and are stable at frequencies of up to 3.4 kHz. Both should be more than sufficient for the purpose. The inductances in the LTSpice model are rough estimates computed from the transformer's winding numbers, dimensions, and using a standard material constant.

On the lower left, an input voltage controlling the pulse level is expected at Vref, and may be generated by RC-smoothing a 3.3V PWM signal. This result should be in the range of 0.3V to 1.3V, and is fed to an op-amp, which serves as impedance decoupler and doubles the voltage on the way.

Transistor Q1, a TIP41, to the right of the op-amp is operated in its linear regime and serves as a current controller. The higher the input level voltage Vref (green), the higher the base voltage (red) of the transistor, and in turn the higher the collector-emitter current (blue): at a base voltage of 0.6V it starts to open, and at around 2.6V it sinks the maximum current, see [3] and the figure to the left. Later, the collector-emitter stim current passing through the TIP41 may be measured before resistor R9 using the Arduino's analog-digital converter.

Here are examples of the stage's behavior on full level and for 50, 100, 200, and 500 microsecond PWM pulses (frequencies of 1kHz, 2.5kHz, 5kHz, and 10KHz) on Vdir (grey) and Vdirinv (magenta). On the primary side, pulses with levels of 28V to 65V to either side are generated at the same frequency, with higher voltages occurring at lower frequencies because of the inductors' latency. The input current drawn (blue) is around 1.8A, with less than 100mA in alternating directions on the output stage (red). Note that the net output current over a period is zero.

Two alternating 50 microsecond pulses generate 100 microsecond pulse with zero average current on the output. A voltage level of only 28V (56V delta) is reached because of the inductors' latency.

Two alternating 100 microsecond pulses generate 200 microsecond pulse with zero average current on the output. A voltage level of only 36V (72V delta) is reached because of the inductors' latency.

Two alternating 200 microsecond pulses generate 400 microsecond pulse with zero average current on the output. A voltage level of only 50V (100V delta) is reached because of the inductors' latency.

Two alternating 500 microsecond pulses generate 1 millisecond pulse with zero average current on the output. A voltage level of 65V (130V delta) is reached because of the inductors' latency. This is close enough to the theoretical maximum voltage of 72V (144V delta) we expect at a secondary side voltage of 12V and using half the transformer's secondary side at a 1:6 ratio.

On the software side, clusters of these pulses will later be generated at frequencies of below 300 Hz and with a duty cycle of up to 10% after reading on [1]. This may be achieved by manipulating the PWM signals on Vdir and Vdirinv. Then, the stage draws a maximum of 180mA even if continuously operated and exposes the user to only 18mA.

References

[1] http://www.smartstim.com/forum/index.php
[2] http://eu.mouser.com/ProductDetail/Xicon/42TU003-RC/
[3] http://pdf.datasheetcatalog.com/datasheet2/e/0ldok1yf92ap6kg5ei3lsiyjfuyy.pdf